CHAMP-WB

CHAMP-WB-DRFM

The CHAMP-WB Signal Processing Engine couples the dense processing resources of a single large Xilinx Virtex-7 FPGA with two high-bandwidth mezzanine sites on a rugged 6U OpenVPX (VITA 65) form factor module. The CHAMP-WB Signal Processing Engine is targeted specifically at wide-band, low latency applications that require large FPGA processing, wide input/output requirements, with minimal latency. When combined with the TADF-4300 module, featuring 12 GS/s 8-bit ADC technology and 12 GS/s 10-bit DAC technology from Tektronix, an extremely high performance wide-band DRFM system can be created which is three times the capability of any COTS. The combined card-set is called the CHAMP-WB-DRFM.

The CHAMP-WB couples the dense processing resources of a single large Xilinx Virtex-7 FPGA with two high-bandwidth mezzanine sites on a rugged 6U OpenVPX (VITA 65) form factor module.

CHAMP-WB Signal Processing Engine Download Datasheet

to know more visit http://www.cwcdefense.com/products/dsp-fpga/6u-vpx-vxs/champ-wb.html

 

Technical Specifications
  • Single user-programmable Xilinx Virtex-7 FPGAs (X690T or X980T): 8 GB DDR3L SDRAM in two banks
  • One 4-lane Gen3 PCIe connection to a Gen3 PCIe switch
  • I/O: 2x FMCs, 2x enhanced FMC, two x8 Gen3 PCIe (expansion plane host interface), four x4 data plane SERDES, one x4 user plane SERDES, 16 LVDS pairs
  • Sensors for monitoring board power consumption
  • ŠŠSupport for ChipScope Pro and JTAG processor debug interfaces
  • Ruggedization levels: AC 100 CC 200
  • VxWorks® and Linux®

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2018-01-22 02:21:02